-
Enhanced SpeedStep is a
series of
dynamic frequency scaling technologies (codenamed
Geyserville and
including SpeedStep,
SpeedStep II, and
SpeedStep III)...
- SSE2, SSE3, SSSE3,
Enhanced Intel SpeedStep Technology (EIST),
Intel 64, XD bit (an NX bit implementation)
Steppings: M0
Based on Core microarchitecture...
- SSE3, SSSE3,
Enhanced Intel SpeedStep Technology (EIST),
Intel 64, XD bit (an NX bit implementation) Die size: 82 mm²
Steppings: R0
Based on the
Penryn microarchitecture...
-
Intel SpeedStep Technology (EIST),
Intel 64, XD bit (an NX bit implementation),
Intel Active Management Technology (iAMT2)a Die size: 111 mm2
Steppings: L2b...
- size: 13.8 mm × 13.8 × 1.0 mm
Steppings: C0 All
models support: MMX, SSE, SSE2, SSE3, SSSE3,
Enhanced Intel SpeedStep Technology (EIST), XD bit (an NX...
- 143 mm2
Steppings: B2, G0
Based on
Penryn microarchitecture All
models support: MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1,
Enhanced Intel SpeedStep Technology...
- FMA3, F16C, BMI1 (Bit Mani****tion Instructions1), BMI2,
Enhanced Intel SpeedStep Technology (EIST),
Intel 64, XD bit (an NX bit implementation), TXT, Intel...
- MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, F16C,
Enhanced Intel SpeedStep Technology (EIST),
Intel 64, XD bit (an NX bit implementation), TXT, Intel...
- support: MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX,
Enhanced Intel SpeedStep Technology (EIST),
Intel 64, XD bit (an NX bit implementation), TXT, Intel...
- 64 KB L1 cache 512 KB L2 cache (integrated) SSE2 SIMD
instructions No
SpeedStep technology, is not part of the 'Centrino'
package Family 6
model 9 Variants...
