- with a TDP of 165 W. Some new
instruction set extensions: WBNOINVD, CLWB,
RDPID, RDPRU, MCOMMIT. Each
instruction uses its own
CPUID bit.
Hardware mitigations...
- four
cores sharing up to 4 MB L2 cache.
Support for Read
Processor ID (
RDPID) new instruction. A 14 nm
manufacturing process System on a chip architecture...
-
functions are
available in Ring 3. The "core ID"
value read by
RDTSCP and
RDPID is
actually the
TSC_AUX MSR (MSR C000_0103h).
Whether this
value actually...
- CLFLUSHOPT, CLZERO, and PTE
Coalescing — — GMET, WBNOINVD, CLWB, QOS, PQE-BW,
RDPID, RDPRU, and
MCOMMIT — — MPK, VAES — — SGX — — FPUs per core 1 0.5 1 1 0...
- CLFLUSHOPT, CLZERO, and PTE
Coalescing — — GMET, WBNOINVD, CLWB, QOS, PQE-BW,
RDPID, RDPRU, and
MCOMMIT — — MPK, VAES — — SGX — — FPUs per core 1 0.5 1 1 0...
- CLFLUSHOPT, CLZERO, and PTE
Coalescing — — GMET, WBNOINVD, CLWB, QOS, PQE-BW,
RDPID, RDPRU, and
MCOMMIT — — MPK, VAES — — SGX — — FPUs per core 1 0.5 1 1 0...
- CLFLUSHOPT, CLZERO, and PTE
Coalescing — — GMET, WBNOINVD, CLWB, QOS, PQE-BW,
RDPID, RDPRU, and
MCOMMIT — — MPK, VAES — — SGX — — FPUs per core 1 0.5 1 1 0...
- CLFLUSHOPT, CLZERO, and PTE
Coalescing — — GMET, WBNOINVD, CLWB, QOS, PQE-BW,
RDPID, RDPRU, and
MCOMMIT — — MPK, VAES — — SGX — — FPUs per core 1 0.5 1 1 0...
-
Instructions (reserved) 21 22 (pcommit) (PCOMMIT instruction, deprecated)
rdpid RDPID (Read
Processor ID)
instruction and IA32_TSC_AUX MSR amx-bf16 AMX tile...
- CLFLUSHOPT, CLZERO, and PTE
Coalescing — — GMET, WBNOINVD, CLWB, QOS, PQE-BW,
RDPID, RDPRU, and
MCOMMIT — — MPK, VAES — — SGX — — FPUs per core 1 0.5 1 1 0...
