- lahf
POPCNT popcnt SSE3
addsubpd SSE4_1
blendpd SSE4_2
pcmpestri SSSE3
pshufb x86-64-v3 AVX
vzeroall Intel Haswell and
newer Intel "big"
cores (AVX2 enabled...
-
allows for a 1
instruction rotation in Core2 and
later Intel CPUs
using the
pshufb instruction Y. Nir; A.
Langley (May 2015). "ChaCha20 and Poly1305 for IETF...
- from an
offset given by an
immediate value encoded in the instruction.
PSHUFB Packed Shuffle Bytes takes registers of
bytes A = [a0 a1 a2 ...] and B =...
- engine.
Throughput and
latency of many
instructions have improved,
including PSHUFB with 1-cycle
throughput (versus 5
cycles for
Silvermont microarchitecture)...
- Negate/zero/preserve
packed doubleword integers depending on
corresponding sign
PSHUFB mm1, mm2/m64 0F 38 00 /r
Shuffle bytes PMULHRSW mm1, mm2/m64 0F 38 0B /r...
-
require this
feature for
integer operation, for
example instruction like
PSHUFB, PMADDUBSW, PHSUBW, PHSUBD, PHSUBSW, PHADDW, PHADDD,
PHADDSW would require...
- is a
single instruction that
combines the SSSE3
instruction PALIGNR and
PSHUFB and adds more to both. Some
compare it the
Altivec instruction VPERM. It...
