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MXCSR management LDMXCSR,
STMXCSR Cache and
Memory management MOVNTQ,
MOVNTPS, MASKMOVQ, PREFETCH0, PREFETCH1, PREFETCH2, PREFETCHNTA,
SFENCE The following...
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require aligned memory addresses even in VEX/EVEX-encoded forms. 0F 2B /r
MOVNTPS m128,x Yes Yes
MOVNTSS m32,x (AMD SSE4a) No No
MOVNTPD m128,x Yes Yes MOVNTSD...
- MOVAPS/MOVAPD
MOVHLPS MOVHPS/MOVHPD
MOVLHPS MOVLPS/MOVLPD MOVMSKPS/MOVMSKPD
MOVNTPS MOVSHDUP MOVSLDUP MOVSS/MOVSD MOVUPS/MOVUPD x86
instruction listings...
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MOVDDUP MOVHLPS MOVHPS/MOVHPD
MOVLHPS MOVLPS/MOVLPD MOVMSKPS/MOVMSKPD
MOVNTPS MOVSHDUP MOVSLDUP MOVSS/MOVSD MOVUPS/MOVUPD x86
instruction listings v...
- MOVAPS/MOVAPD
MOVDDUP MOVHLPS MOVHPS/MOVHPD
MOVLHPS MOVLPS/MOVLPD MOVMSKPS/MOVMSKPD
MOVNTPS MOVSHDUP MOVSLDUP MOVSS/MOVSD MOVUPS/MOVUPD x86
instruction listings...
