-
stepping F of the AMD K8, and is not
available on
earlier steppings. For
CLZERO, the
address size and 67h
prefix control whether to use AX, EAX or RAX as...
-
CPUID EAX=80000008h:
Feature bits in EBX Bit EBX
Short Feature 0
clzero CLZERO instruction 1
retired_instr Retired instruction count MSR (C000_00E9h)...
- TSME, ADX, SHA, RDSEED, SMAP, SMEP, XSAVEC, XSAVES, XRSTORS, CLFLUSHOPT,
CLZERO, and PTE
Coalescing — — GMET, WBNOINVD, CLWB, QOS, PQE-BW, RDPID, RDPRU...
- TSME, ADX, SHA, RDSEED, SMAP, SMEP, XSAVEC, XSAVES, XRSTORS, CLFLUSHOPT,
CLZERO, and PTE
Coalescing — — GMET, WBNOINVD, CLWB, QOS, PQE-BW, RDPID, RDPRU...
- TSME, ADX, SHA, RDSEED, SMAP, SMEP, XSAVEC, XSAVES, XRSTORS, CLFLUSHOPT,
CLZERO, and PTE
Coalescing — — GMET, WBNOINVD, CLWB, QOS, PQE-BW, RDPID, RDPRU...
- TSME, ADX, SHA, RDSEED, SMAP, SMEP, XSAVEC, XSAVES, XRSTORS, CLFLUSHOPT,
CLZERO, and PTE
Coalescing — — GMET, WBNOINVD, CLWB, QOS, PQE-BW, RDPID, RDPRU...
- TSME, ADX, SHA, RDSEED, SMAP, SMEP, XSAVEC, XSAVES, XRSTORS, CLFLUSHOPT,
CLZERO, and PTE
Coalescing — — GMET, WBNOINVD, CLWB, QOS, PQE-BW, RDPID, RDPRU...
- TSME, ADX, SHA, RDSEED, SMAP, SMEP, XSAVEC, XSAVES, XRSTORS, CLFLUSHOPT,
CLZERO, and PTE
Coalescing — — GMET, WBNOINVD, CLWB, QOS, PQE-BW, RDPID, RDPRU...
- TSME, ADX, SHA, RDSEED, SMAP, SMEP, XSAVEC, XSAVES, XRSTORS, CLFLUSHOPT,
CLZERO, and PTE
Coalescing — — GMET, WBNOINVD, CLWB, QOS, PQE-BW, RDPID, RDPRU...
- XSAVEC/XSAVES/XRSTORS, and
CLFLUSHOPT instructions. ADX support. SHA support.
CLZERO instruction for
clearing a
cache line.
Useful for
handling ECC-related Machine-check...
